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Extra resources for Advanced FDTD methods : parallelization, acceleration, and engineering applications

Sample text

Unpacks single-precision values from low halves. Cache Control: prefetchT0 - Fetches a cache line of data into all levels of cache. prefetchT1 - Fetches a cache line of data into all but the highest levels of cache. prefetchT2 - Fetches a cache line of data into all but the two highest levels of cache. prefetchNTA - Fetches data into only the highest level of cache, not the lower levels. sfence Guarantees that all memory writes issued before the sfence instruction are completed before any writes after the sfence instruction.

You can also put an absolute distance between the dipole and the absorbing boundary as the white space. However, the number of cells inside white space will vary with the local cell size. It is not a good choice for the practical applications Electromagnetic Simulation Techniques 53 since we need to know the number of cells to estimate the accuracy, simulation time, and memory usage. Since the shape of the dipole is a long cylinder, the computational domain will have a similar shape if we use the same size of white space around the dipole.

We use the VALU through the SIMD instruction set to accelerate the parallel FDTD method. 1 = + = CPU architecture including the floating-point unit (FPU) and the vector arithmetic logic unit (VALU). The Pentium 4 processor, and each core on a Pentium D CPU, could execute one SIMD instruction every two clock cycles. Intel streamlines the SSE execution unit, making it 128 bits wide throughout. In addition, Core 2 offers three SSE execution units. The net result is that 128-bit-wide SSE instructions can be FDTD Optimization and Acceleration 21 executed in a single clock cycle.

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